I. Field
The present disclosure generally relates to systems and methods of scan testing.
II. Description of Related Art
Generally, an integrated circuit may include multiple digital logic circuits. One type of digital logic circuit is a flip-flop, which is a circuit that can be switched between two states. Flip-flop circuits are a common type of sequential circuit element used to build digital systems. Accordingly, flip-flop circuits may have an impact on both power and performance for such systems.
Modern integrated circuits usually incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability. Typically, the DFT structures are based on a scan design, where scan test data is provided to a test pin or where a plurality of externally accessible scan chains are embedded into the integrated circuit. When the scan chain is embedded, the scan chain may include one or more scan cells coupled in series, with each scan cell including a flip-flop or a latch. Typically, scan test design is used in conjunction with fault simulation and combinational ATPG (automatic test pattern generation) to generate manufacturing and diagnostic test patterns for production test and prototype debug processes.
To provide DFT functionality, a circuit may have a test input, which can be accessed during a testing mode and which may be tied to a logic level during normal non-test operation. Test logic, such as a multiplexer, may be introduced to select between modes and to provide a data pattern to a logic circuit to be tested by passing the data pattern through the chain. The resulting output of the logic circuit provides an indication of faults present in the logic circuit.
To test a logic circuit, the test logic provides test data to an input of the logic circuit. Unfortunately, to provide the data to the input, the test logic, such as a multiplexer, is typically placed within the data path of the logic circuit and may unnecessarily consume power during normal non-test operation. Moreover, such test logic may introduce delays in the data path of the logic circuit, and the delays tend to reduce the performance of the logic circuit.
Other sequential technologies, including pulsed latches, have been used to reduce delay. While pulsed latches may reduce the delay in the data path of the logic circuit, pulsed latches tend to consume more power and are typically less robust than flip-flops.
Accordingly, it would be advantageous to provide a logic circuit with an improved test logic that reduces power loss and delays while maintaining DFT compatibility.